A new technical paper titled “PPAC Driven Multi-die and Multi-technology Floorplanning” has been published by researchers from Texas A&M University and Duke University. The paper, which focuses on heterogeneous integration, introduces a systematic study of multi-die and multi-technology floorplanning. Unlike traditional approaches, this study considers factors such as performance, power, and cost in addition to area and wirelength, emphasizing the importance of technology selection.
The researchers developed simulated annealing and reinforcement learning techniques to optimize multi-die and multi-technology floorplanning. Experimental results demonstrated that these techniques outperformed a naive baseline approach. The paper is available on arXiv and was published in February 2025.
This groundbreaking research sheds light on the complexities of floorplanning in heterogeneous integration scenarios, where different dies utilize different technologies. By taking a holistic approach that incorporates various factors into the floorplanning process, the researchers have shown significant improvements in efficiency and performance.
The findings of this study have the potential to revolutionize the way multi-die and multi-technology floorplanning is approached in the field of semiconductor technology. With the development of new techniques and methodologies, engineers and researchers will be better equipped to optimize floorplanning across multiple dies and technologies, leading to more efficient and cost-effective solutions in the future.
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